Wafer-level packaging slices MEMS' costs

The manufacture of microelectromechanical systems (MEMS) has rapidly moved from “a little lonely device,” the accelerometer used in air bags, to a multitude of devices. Applications for MEMS range from Wii games and night-vision cameras to microfluidic cell therapies for various diseases. (See related story here.)Wafer-level packaging (WLP), which reduces costs, is partly responsible for this proliferation.

“As you move forward in the consumer space, wafer-level packaging becomes a high priority because it enables footprint reduction, cost reduction and higher-quality products with through-wafer connectivity and wafer-to-wafer bonds,” said Kevin Mach, business development manager at Micralyne Inc., a MEMS foundry in Edmonton, Alberta. “By shifting traditional back-end processes into the front-end fabrication process, you can reduce the number of single process steps.”

Figure 1: These suspended mass resonator MEMS will be packaged at the wafer level in an ultrahigh vacuum (<1 mTorr) to enable particle detection in fluids with femtogram resolution. Illustration courtesy IMT.

“The more you can do at the wafer level, the lower the cost,” said E. Jan Vardaman, a packaging consultant and president of TechSearch International Inc., Austin, Texas. Because MEMS packaging costs account for 40 to 70 percent of system cost, foundries are eager to implement WLP.

The MEMS industry is also embracing multiwafer stacking of MEMS-on-MEMS or MEMS-on-semiconductors. “We currently have seven multiwafer projects—four projects using four wafers and two projects using five wafers,” said Craig Trautman, vice president of business development at IMT, a foundry in Santa Barbara, Calif. The ability of MEMS foundries to produce yielding multiwafer devices is a function of the maturity of their off-the-shelf intellectual property and production processes. “Process complexity is increasing, but we can absorb that, partly because the wafer bonding techniques are so well characterized,” added Trautman.

Device in motion

MEMS packages must provide electrical connection, physical protection and thermal management (like semiconductors), in addition to an interface for the mechanical or sensing functions.

For instance, the MEMS device might need to be open to the environment, as is the case with silicon microphones, chemical sensors and pressure sensors. Other MEMS devices, such as RF (radio frequency) filters and oscillators, require hermetic sealing to protect them from contamination and moisture. Still others require a level of vacuum in the cavity.

“Ultrahigh vacuum, in the 10 millitorr or less range, is required for very-high-performance gyroscopes and infrared sensors, including bolometers and thermopiles,” said Jay Mitchell, president and co-founder of ePack Inc., Ann Arbor, Mich.

Often, this vacuum environment enables the MEMS device to perform extreme functions. For instance, in a commercial sensor (Figure 1), a microfluidic channel embedded in a resonating cantilever is used to measure particle mass. The change in resonant frequency when the particle enters the cantilever tip creates a measurement of mass at the femtogram (10-15 g) level. This measurement is dependent on a very-high quality factor, and can only be accomplished with a cantilever in an ultrahigh vacuum. (A Q factor for a resonator or oscillator indicates energy loss relative to stored energy—a ratio of bandwidth to center frequency.)

One bond, one app?

MEMS foundries typically process 150mm wafer substrates in quantities of hundreds per year (low volume) to several thousands per year (medium volume) to hundreds of thousands or more per year (high volume). “A big reason people are switching to 200mm tools is not so much to meet production demands,” Mach noted, “but to utilize semiconductor capabilities.”

In a WLP process, the MEMS device is fabricated on the host wafer, often with through-silicon vias (TSVs), while a cap wafer is patterned to form microcavities (Figure 2). The wafers are carefully aligned and bonded using one or more methods (Table 1).** “Selection of the bonding process is a function of die size, temperature, cost, need for hermeticity and process complexity,” said Trautman. “Thermal budget is a big deal, and if it’s a multiwafer product, you have to be concerned with reflow, hermeticity and absolute pressure.”

Figure 2: Through-silicon via with connective pads (upper left). Wafer bonded via fusion bonding and eutectic bonding (right), and an illustration of a vacuum wafer-level-packaged device (bottom). Images courtesy Micralyne.

The most mature bonding methods are glass frit, fusion and anodic. More recently, metal alloy and eutectic bonding have gained in popularity, particularly for lower-temperature applications. Foundries are using gold-tin (Au-Sn) eutectic bonding for applications such as a silicon-based resonator, which was recently developed by Seiko Instruments Inc., based in Chiba, Japan, and the Institute of Microelectronics, Singapore. Au-Sn eutectic bonding features simple deposition and patterning, is resistant to roughness and is inherently hermetic. Thermocompression bonding of gold-to-gold (Au-Au) at 300° C can also achieve hermeticity.

MEMS WLP can incorporate TSVs or lateral feedthroughs to connect to the printed circuit board. TSVs are critical enablers for multiwafer devices (Figure 3), interposers and magnetic devices.

Said Mitchell, “With through-silicon vias, you can save in die size and also save further up the value chain through integration by ‘flip chipping’ the device instead of wire bonding.” (With flipchip packaging, the active area of the chip faces downward and is bonded to the package; this method allows for more interconnects than wire bonding.) Trautman added that achieving nearly perfect yield with copper through-silicon vias has proven to be a significant challenge for the MEMS industry, but one it is meeting.

Next-gen processes

Since the bond line around MEMS devices does occupy valuable silicon real estate, it is possible that thin-film encapsulation techniques, combined with WLP (Figure 4), will be used more. Thin-film encapsulation is being applied to RF applications, where low insertion loss and low resistance are important.

Figure 3: A cell sorter chip (above) has three wafers dedicated to refractive and reflective optics (top), microfluidics (middle) and actuation (bottom). Completed chip (right). Illustration courtesy IMT.

Figure 4: A nickel-plated capping wafer eliminates the footprint constraints of die-size sealing ring, while still meeting RF MEMS requirements. Illustration courtesy KFM Technology.

“This approach has the advantage of being able to deposit the smallest cap possible, which reduces parasitics on an RF device,” said Fabrice Verjus, chief technology officer for KFM Technology in Yvette, France. The technology, which involves adhesive bonding with benzocyclobutene polymer and a nickel-plated thin film microcap, can package together MEMS switches, fixed capacitors and high-Q inductors. µ

About the author: Laura Peters is a freelance writer specializing in micromanufacturing and renewable energy technologies. E-mail: lpeters40@gmail.com.

** See “Overview of wafer level packaging technology for MEMS applications,” by Michael Shillinger, MEMS Investment Journal, Nov. 18, 2010.

Table 1: Comparison of common bonding techniques

Table courtesy IMT.